Field
The disclosure relates generally to power supply circuits and methods and, more particularly, to buck type converters with a zero-cross comparator, circuit and a method thereof.
Description of the Related Art
Switching Mode Power Supply (SMPS) converter power supply stage and low dropout (LDO) regulators are a type of voltage regulators used in conjunction with semiconductor devices, integrated circuit (IC), battery chargers, and other applications. Low dropout regulators (LDO) can be used in digital, analog, and power applications to deliver a regulated supply voltage.
An example of known to the inventor, a Switching Mode Power Supply (SMPS) converter power stage including a zero-cross comparator is shown in FIG. 1. The SMPS converter 10 has an output signal VOUT 20, and a ground connection 30. The output stage comprises of a series. inductor 40, an output capacitor Cout 50, and resistor load Rload 60. A series PMOS switch 70 has a control network 75, and a second NMOS switch 80 has a control network 85. A zero cross comparator 90 has inputs connected across the NMOS switch 80.
The control circuit (not shown) provides the control signals for two switches which are in this case realized as PMOS 70 and NMOS 80 transistors. The operation is in Discontinuous Conduction Mode (DCM). In some buck converter designs, the buck works at a fixed switching frequency. Each clock cycle starts with turning the PMOS 70 on and charging the coil during the tr time. Then the PMOS is turned off and the NMOS 80 is turned on instead. In this moment the control circuit is waiting for output of zero-crossing comparator ZC 90. This comparator triggers when the current in the coil reaches zero level. At this moment the NMOS 80 is turn off and no current through the coil is flowing. The control circuit (not shown) is waiting for next clock signal to start next switching period. The control circuit (not shown) provides the control signals for two switches which are in this case realized as PMOS and NMOS transistors.
FIG. 2 shows the timing diagram 200 for the circuit described in FIG. 1. The buck works at a fixed switching frequency. Each clock cycle starts with turning the PMOS 210 on and charging the coil during the tr time. Then the PMOS 210 is turned off and the NMOS 220 is turned on instead. The OFF state 230, inductor current IL 240, node voltage VLX 250 and zero-crossing comparator 260 are also shown in the timing diagram. In this moment the control circuit is waiting for output of zero-crossing comparator ZC 260. This comparator triggers when the current in the coil reaches zero level. At this moment the NMOS is turn off and no current through the coil is flowing. The control circuit is waiting for next clock signal to start next switching period. From the description above the importance of the zero-crossing comparator is obvious. An ideal NMOS turning off is shown in FIG. 2—period A. Two possible malfunctions of the zero-crossing comparator are shown in periods B and C.
If the NMOS is turn off too late, as is depicted in period B, the current in the coil goes negative and the voltage on LX node has to go above the VIN, turns on the parasitic diode in the PMOS and push the charge in to the VIN till the coil current reach zero. This is the worst response because the higher drop on the parasitic diode increases power consumption and decreases valuable efficiency of the converter and the current is actually taken from the output and pushed back in to the input.
On the other side, if the NMOS is turned off too early, as is depicted in part C, the current in the coil goes through the parasitic diode of the NMOS transistor which increases losses because the voltage across the diode is higher than the voltage across NMOS in ‘on’ state. Hence, the more precise turning off the NMOS the better efficiency is achieved.
The above described circuit of FIG. 1 has some undesirable response features. First, the standard zero-crossing comparator evaluates a small input voltage, requiring design complexity and a non-simple design solution. Additionally, special techniques to minimize the offset exist. For improvement, trimming is usually required. Strict requirements also exist for the comparator. The comparator must be sufficiently fast which leads to higher power consumption. Additionally, the comparator is connected to very noisy circuit and system nets which make the design implementation even more difficult.
U.S. Pat. No. 6,396,250 to Bridge, describes a control method to reduce body diode conduction and reverse recovery losses. A DC-to-DC converter to convert a first DC voltage to a second DC voltage includes a first switch connected to input the first DC voltage, a second switch, the first switch and the second switch being controlled by an input signal to generate the second DC voltage, the first switch and the second switch being connected to a control reference, and a control circuit to control the delay of the input signal by monitoring the control reference around an optimal delay point.
European Patent EP 1,639,693 to Dikken et al., describes dead time control in a switching circuit. A switching circuit where adjustment means adjust the length of the dead time period based on a voltage difference is described.
U.S. Pat. No. 7,570,038 to Yang, describes a control circuit to reduce reverse current of synchronous rectifier, This describes a circuit which minimizes the reverse current in a power control circuit.
European Patent EP 2,214,298 to Satou et al., describes a DC-DC converter and switch control circuit. A dc-to-dc converter has a means of controlling the transition time between the on-state and off-state of the network.
In these embodiments, the solutions to improve the response of a buck converter, and more specifically utilize various means to address transitioning and dead time is discussed.